The Olympus-SoCâ„¢ Netlist-to-GDSII system comprehensively addresses the performance, capacity, time-to-market, power, and variability challenges encountered at the leading-edge process nodes. It is a complete physical design implementation tool for the complex multi-patterning and FinFET requirements of advanced process technologies.

Olympus-SoC provides the highest capacity in the industry, with a very compact and scalable database capable of handling designs with hundreds of millions of instances. Its low-power suite enables both leakage and dynamic power reduction throughout the flow, and power-aware clock tree synthesis.



Olympus-SoC avoids unpredictability in sign-off ECO loops, eliminates performance-killing pessimism, and speeds the time-to-tapeout by considering all scenarios concurrently, from floorplanning to GDSIII-out


Features :

Low Power

  • UPF 2.0 (IEEE 1801) based multi voltage flow
  • Support for gas station methodology and always-on-buffering
  • Power-aware buffering and sizing
  • Power state table (PST) based advanced buffering
  • Support for level shifters, isolation cells, and retention registers
  • Distributed and ring style multi-threshold (MTCMOS) switch cell insertion
  • Hierarchical UPF support
  • Concurrent multi-Vt optimization
  • Power aware CTS featuring cloning, restructuring, and slew shaping
  • Concurrent power and timing optimization for all corner/mode/power scenarios
Advanced Nodes

  • Comprehensive multi patterning and FinFET support
  • Native coloring, verification and conflict resolution engines
  • DRC, double/multi patterning, and DFM rule support for all leading foundries
  • Pattern matching and recommended rules support
  • Variation-aware timing and SI driven routing
  • Automated, intelligent prevention of DRC/DFM issues
  • Integrated Calibre sign-off engines for sign-off physical verification
  • Automatic fixing of DRC and DFM violations during physical design